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32-Lane PCIe 3.0 Packet Switch from Diodes Incorporated Addresses Fan-Out and Multi-Host Connectivity
The basic architecture of the PI7C9X3G1632GP consists of 2 tiles that each feature 8 ports and 16 lanes, which enables it to support 32 lanes of SERDES in configuration options that span from 2 ports all the way up to 16 ports. To address a diverse range of potential applications, such as port fan-out and connection to multiple hosts, different port types can be assigned. These include upstream, downstream, and cross-domain end-point (CDEP) ports.
Multiple DMA channels are embedded into the PI7C9X3G1632GP to enable more efficient data communication between the host/hosts and connected endpoints. The low packet forwarding latency exhibited (<150ns typical) means that high performance data transmissions can be achieved. Integration of a PCIe 3.0 clock buffer helps reduce the overall bill-of-materials costs and simplifies the implementation process.
The incorporation of further features, such as advanced error reporting, error handling and end-to-end data protection, are all pivotal in ensuring ongoing transmission reliability. In addition, operational conditions are monitored using the built-in thermal sensor.
Advanced power management functions enable significant energy savings, which enables the PI7C9X3G1632GP to operate across the industrial temperature range of -40°C to 85°C and allows it to be used in a broad array of applications.
The PI7C9X3G1632GP packet switch is supplied in a 676-pin FCBGA package with a 27mm x 27mm footprint. It is available at
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