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8-Port PCIe 3.0 Packet Switch from Diodes Incorporated Provides Design Flexibility and Power Savings
The proprietary architecture employed in the PI7C9X3G808GP packet switch provides enhanced flexibility and performance. Multiple port / lane width combinations are available, as well as cross-domain end-point (CDEP) arrangements. Thanks to its CDEP capabilities, the PI7C9X3G808GP supports fan-out and dual-host connectivity.
The built-in PCIe 3.0 clock buffer allows for a reduction in the overall component count and helps to curb BOM costs. This integrated buffer is unique to the industry, because of its low-power operation. Three different reference clock options can be used: common, separate reference no spread (SRNS), and separate reference independent spread (SRIS). Multiple direct memory access (DMA) channels have been embedded into the switch, in order to make communication between host (or hosts) and connected end-points as efficient as possible.
Features include error-handling, advanced error reporting, and end-to-end data protection with error correction - key functionality in terms of reliability, availability, and serviceability (RAS). The advanced power management means that this switch is aligned with the most stringent energy-saving requirements. Unused hot-pluggable ports are kept in a low-power state until needed. Under full load conditions and 80°C junction temperature, the PI7C9X3G808GP will draw only 2.9W of power.
Diodes Incorporated’s PI7C9X3G808GP is supplied in a high-performance flip-chip package, with 196-ball BGA format. It has dimensions of 15mm x 15mm. This next generation packet switch has a unit price of
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